1. Field of the Invention
The present invention relates to integrated circuit-type devices generally and more particularly to a sequential-access and random-access dual-port memory buffer.
2. Description of the Related Art
A FIFO (first-in-first-out) buffer functions as a shift register having an additional control section that permits input data to "fall through" to the first vacant stage. In other words, if there is data stored in the FIFO buffer, it is available at the output even though all of the states are not filled. Thus, in effect, a FIFO buffer functions as a "variable-length" shift register, the length of which is always the same as the data stored therein.
Although shift registers may be used, of late, many FIFO buffers are implemented with dual-port random-access memories (RAMs) and counters. For additional information regarding FIFO buffers, the reader is referred to the U.S. Pat. No. 4,750,149.
As such, FIFO buffers are particularly suited for use in applications in which there is a need to compensate for differences in the rate of flow of data. For example, FIFO buffers are particularly suited for use in storing data which is to be written onto a disk and/or which has been read off of a disk; for use in storing data which is to be transmitted to a local area network (LAN) and/or which has been received from a LAN; and for use in storing data which is to be printed.
Computers of the type which are designated IBM Personal Computer (IBM PC) and PC/XT by International Business Machines (IBM) Corporation include an interface bus for receiving, external, plug-in cards. This (PC/XT) bus is relatively limited, permitting the transfer of only eight-data bits at one time. In computers of the type which are designated PC/AT by International Business Machines (IBM) Corporation the (PC/XT) bus is extended, permitting the simultaneous transfer of sixteen-data bits. This (PC/XT/AT) bus is further extended in computers of the type which are commonly designated EISA.
Proper connection to the EISA bus requires a number of specific signals each having specific timing. These signals are provided by EISA bus interface devices of the type which are designated 82355 by the Intel Corporation. Unfortunately, the above mentioned EISA bus interface devices are intended for connection between the EISA bus and a sequential-access (buffer) device, which provides specific signals each having specific timing.
Thus, a need exists for a buffer suitable for connection between a random-access (microprocessor-type) device and a sequential-access device. Preferably, to the random-access device, the buffer should appear as a random-access-memory RAM cell array. To the sequential-access device, the buffer should appear as a sequential-access buffer. Preferably, the buffer should, additionally, provide the signals necessary for connection to the above-mention EISA-bus-interface-type devices.